MVAPICH/MVAPICH2 Project
Ohio State University



Westmere-EP | InterNode | Performance | Network-Based Computing Laboratory

Performance numbers of MVAPICH2 on Westmere-EP Architecture (05/06/13)

  • Experimental Testbed: Each node of our testbed has 12 cores (2.8 GHz dual hex-core) and 24 GB main memory. The CPUs based on Westmere-EP architecture and run in 64 bit mode. The nodes support 16x PCI Express Gen2 interfaces and are equipped with QLogic QDR HCAs with PCI Express interfaces. The nodes are connected using a QLogic QDR InfiniBand switch. The operating system used was TOSS 2.0. The processes were bound to core 1 on both nodes.
  • MVAPICH2 currently delivers one-sided put latency of 5.45 microseconds for 4 bytes, one-sided get latency of 8.82 microseconds for 4 bytes, one-sided put bandwidth up to 3235.19 Million Bytes/sec, one-sided get bandwidth up to 2283.27 Million Bytes/sec and put bidirectional bandwidth upto 4418.24 Million Bytes/sec on the above testbed. (1 Mega Byte = 1,048,576 Bytes; 1 Million Byte = 1,000,000 Bytes)