MVAPICH/MVAPICH2 Project
Ohio State University



Westmere | InterNode | Performance | Network-Based Computing Laboratory

Performance numbers of MVAPICH2 on Westmere Architecture (05/06/13)

  • Experimental Testbed: Each node of our testbed has eight cores (2.53 GHz dual quad-core) and 12 GB main memory. The CPUs based on Westmere architecture and run in 64 bit mode. The nodes support 16x PCI Express Gen2 interfaces and are equipped with Mellanox ConnectX-2 QDR HCAs with PCI Express interfaces. The nodes are connected using a 144 port Mellanox QDR InfiniBand switch. The operating system used was RedHat Enterprise Linux Server release 5.4 (Tikanga). The processes were bound to core 1 on both nodes.
  • MVAPICH2 currently delivers one-sided put latency of 2.55 microseconds for 4 bytes, one-sided get latency of 5.32 microseconds for 4 bytes, one-sided put bandwidth up to 3355.20 Million Bytes/sec, one-sided get bandwidth up to 3371.96 Million Bytes/sec and put bidirectional bandwidth upto 6342.24 Million Bytes/sec on the above testbed. (1 Mega Byte = 1,048,576 Bytes; 1 Million Byte = 1,000,000 Bytes)