MVAPICH/MVAPICH2 Project
Ohio State University



Sandy Bridge | IntraNode | Performance | Network-Based Computing Laboratory

Intra-node performance numbers of MVAPICH on Sandy Bridge Architecture (04/30/12)

  • Experimental Testbed: Each node of our testbed has two 8-core 2.6 GHz Intel Xeon E5-2670 (Sandy Bridge) processors and 32 GB main memory. The nodes support 16x PCI Express Gen3 interfaces and are equipped with Mellanox ConnectX-3 FDR HCAs with PCI Express Gen3 interfaces. The operating system used was RedHat Enterprise Linux Server release 5.4 (Tikanga). The processes were bound to core 1 on both nodes
  • MVAPICH currently delivers one-way latency of .30 microseconds within the socket for 4 bytes and .86 microseconds between sockets for 4 bytes; unidirectional bandwidth upto 10407.99 Million Bytes/sec within the socket and 5125.32 Million Bytes/sec between sockets; between sockets on the above testbed. (1 Mega Byte = 1,048,576 Bytes; 1 Million Byte = 1,000,000 Bytes)
  • Processes were mapped onto cores 1 and 2 to take the intra socket numbers and onto 1 and 9 to take the inter socket numbers.